1. Field of the Invention
The present invention relates to information handling systems, and more particularly to information handling systems requiring data block transfer such as between caches or between caches and main memory.
2. Prior Art
In the prior art there are many techniques for handling data block transfers. However, the prior art techniques all have one or more shortcomings which result in a slower block transfer than is desirable.
Examples of prior art cache memory management systems are described in U.S. Pat. No. 5,091,846 entitled "Cache Providing Caching/Non-caching write-through and Copy Back Modes for Virtual Addresses and Including Bus Snooping to Maintain Coherency" and U.S. Pat. No. 5,255,384 entitled "Memory Address Translation System Having Modifiable and Non-modifiable Translation Mechanisms." The two patents which seem to disclose different aspects of the same system, are directed to a cache and a memory address translation system.
The 846 Patent teaches a computing system, having a cache memory management system, which provides selectable access modes for addressable memory, providing cachable and non-cachable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation logic of the cache memory management system. The system provides high speed virtual to real address translation along with associated system tag data defining access priorities and access modes associated with each respective address translation.
The 384 patent which deals with cache memory management system features a high speed virtual to real address translation technique. Address translation logic including mutually exclusive modifiable and non-modifiable translation logic selectively provides real address output in response to the externally supplied virtual address from a processor. A cache controller selectively accesses main memory on cache memory misses to load translation information and other data from main memory to the cache memory.
Although the patents generally teach cache memory systems and address translation for use in cache memory systems, neither patent teaches the invention as taught and claimed herein.
An article published in the IBM Technical Disclosure Bulletin Volume 26, No. 2, July 1983, entitled "Optimized Data Transfer Function for Memory Cell Map Buffers" teaches a technique for optimizing data transfer using registers which store a first failing address and a last failing address and comparators for determining whether a particular address falls within the first and last address or outside of the range of the first and last address.
Although the TDB article contains some fundamental similarities to a portion of the present invention as shown and claimed herein, the TDB article does not provide a technique for transferring only a modified segment of a data block as is shown and claimed herein.